Chip Select / Address Decoder

Address decoding has been a fundamental architectural element of computers since the 1950s. Early stored-program machines used rotary switches and patch-cords to select different memory banks; the first integrated address decoders appeared in the 1960s as TTL logic matured. The 74LS138 3-to-8 decoder (Texas Instruments, early 1970s) became the standard workhorse chip for small-system address decoding — combining three address lines plus three enable lines into one of eight active-low chip-select outputs.

As address bus widths grew from 16 bits (8080, Z80, 6502) to 20 bits (8086), 24 bits (68000), and beyond, dedicated decoder logic became impractical. Programmable logic devices (PALs and GALs in the 1980s, CPLDs and FPGAs in the 1990s) replaced discrete decoders with configurable chip-select equations. Modern SoC designs embed address decoding directly into memory controllers and bus matrices (AXI interconnects, AMBA fabric), but the underlying math — high-order address bits must match the device base, low-order bits index within the device — is unchanged since the TTL era.

Alignment to power-of-2 boundaries minimizes decoder complexity: a 256-byte device at address 0xE000 needs only 8 bits of comparison, but at address 0xE010 it would require a full 16-bit comparator. This is why operating systems and linker scripts align memory-mapped peripherals to natural boundaries — the hardware cost drops precipitously.

Enter a base address in hex, device size (bytes, with K/M suffixes), and the system\'s address bus width. The tool computes the end address, number of offset bits (low-order pass-through), number of compare bits (high-order that must match base), and the compare mask.

The resulting values let you implement the chip-select equation in discrete logic (74LS138 + AND gates), in a PLD/GAL, or in an FPGA. For non-power-of-2 sizes (rare but possible), the tool rounds up to the next power of 2 and notes the unused range. All math runs client-side; no values leave your browser.