FIR Filter Coefficient Quantization Calculator
Estimate fixed-point coefficient word-length needed for an FIR filter to meet a given stopband attenuation after quantization.
How to Use
- Enter required stopband attenuation (dB) and filter length N.
- Tool estimates minimum coefficient word-length (bits) to preserve the stopband spec.
Show Work
Formulas
History of Fixed-Point Filter Design
Alan Oppenheim and Ron Schafer's 1975 textbook Digital Signal Processing formalized coefficient-quantization analysis - showing that filter stopband attenuation is limited by ~(6B - 4) dB where B is the coefficient word length. Texas Instruments' TMS32010 (1982, first commercial DSP chip) had 16-bit coefficient storage, limiting filters to ~90 dB stopband. Modern audio DSPs and FPGAs use 18-32 bit coefficients for professional audio applications.
About This Calculator
Enter required stopband attenuation (dB) and FIR filter length (number of taps). The tool estimates minimum coefficient word-length B = (A_s + 4 + 10·log(N))/6 and recommends nearest hardware-friendly word size (16, 18, 24 bits).
For real designs, use Matlab\'s fxpconvert, Python\'s scipy.signal.firwin2 + quantization, or your FPGA vendor\'s filter-synthesis tool. This is a first-pass estimate for specification purposes. Everything runs client-side.
Frequently Asked Questions
Why quantize?
Fixed-point DSPs and FPGAs use finite-precision coefficient storage. Rounding off bits distorts the ideal frequency response — especially stopband. More bits = better fidelity but more hardware.
Rule of thumb?
Word length B bits gives ~(6B − 4) dB stopband attenuation limit. For 80 dB: need ≥ 14-bit coefs. For 100 dB: ≥ 18-bit. Adds ~6 dB per extra bit.
Floating point?
Single-precision IEEE 754 gives ~24 mantissa bits → ~140 dB — more than any practical filter needs. Double precision is overkill for DSP. Fixed-point (Q format) wins on power and throughput.
Common Use Cases
Audio ADC Decimator
96 dB target: use 18-20 bit coefficients on Q1.17 format.
Software Radio
80 dB adjacent-channel rejection: 16-bit coefs are minimum.
FPGA Implementation
Xilinx DSP48 multiplier: 18×18 bit → 80+ dB filter achievable.
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