LFSR Maximal Period Calculator
Compute maximum period of a Linear-Feedback Shift Register (LFSR) and list maximal-length tap polynomials for common bit widths.
How to Use
- Enter number of shift register bits (width).
- Tool returns maximal period 2^N - 1 and a standard maximum-length polynomial.
Show Work
Max-Length Taps
History of the LFSR
Solomon Golomb's 1967 book Shift Register Sequences codified the theory of linear-feedback shift register pseudo-random sequences, building on Marsh and Zierler's 1940s work on maximal-length polynomials. CCSDS standardized PRBS-7, PRBS-15, PRBS-23, and PRBS-31 for spacecraft telemetry in the 1970s. LFSRs became ubiquitous in consumer electronics as CRC generators (Ethernet's CRC-32 uses a 32-bit LFSR) and as PN-code generators in CDMA cellular and GPS.
About This Calculator
Enter register width N (2-32 bits). The tool returns maximal period 2^N − 1, a standard max-length tap pair (from the Zierler-Brillhart tables), and the corresponding polynomial in hex.
LFSRs are everywhere in digital systems: CRC computation, pseudo-random test patterns (PRBS-7 through PRBS-31), spread-spectrum chipping codes, and legacy hardware PRNGs. For cryptographic randomness, LFSRs alone are too predictable — use cryptographic PRNGs (ChaCha20, AES-CTR-DRBG). Everything runs client-side.
Frequently Asked Questions
What is an LFSR?
Linear-Feedback Shift Register: a shift register with XOR feedback taps. Produces pseudo-random binary sequences. Core of CRC generators, pseudo-noise sequences for spread-spectrum, and simple hardware PRNGs.
Maximal length?
An N-bit LFSR produces at most 2^N - 1 unique states before repeating (the all-zero state is excluded). A maximal-length tap polynomial hits all 2^N - 1 states in a single cycle.
Uses?
Pseudo-noise sequence generation (GPS C/A code uses 10-bit LFSR giving 1023-chip sequence). CRC code generation. Simple hardware random-number sources. Bit-error-rate test pattern generation.
Common Use Cases
GPS C/A Code
10-bit LFSR × 2, XOR gives 1023-chip Gold code per satellite.
PRBS Tester
PRBS-7 (2^7 − 1 = 127 bit pattern) for Ethernet BER test.
CRC-32
32-bit LFSR with polynomial 0x04C11DB7 — Ethernet CRC.
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