MOSFET Gate Drive Calculator

Calculate gate drive current, switching losses, and gate resistor sizing for MOSFETs in switching applications. Covers gate charge Qg, rise/fall times, and power dissipation.

Calculator Electronics Updated Apr 18, 2026
How to Use
  1. Enter gate charge (Qg from datasheet), gate drive voltage, and target switching time.
  2. Peak drive current = Qg / t_sw.
  3. Gate resistor limits current; too small risks ringing, too large slows switching.
  4. Switching losses scale with frequency, Vds, Id, and switching time.
Input
nC
V
ns (µs, ms OK)
Hz (kHz, MHz OK)
V
A
Presets
Drive Summary
Peak Gate I
A
Gate Resistor
Ω
Switching Loss
W
Drive Power
mW

Show Work

Enter values to see the gate-drive calculation.

Formulas

Peak Gate Current
Ig,peak = Qg / tsw
Sized by driver capability.
Gate Resistor
Rg = Vgs / Ig,peak
Limits peak current to target.
Drive Power
Pd = Qg × Vgs × fsw
Average gate-drive dissipation.
Switching Loss
Psw = ½ × Vds × Id × tsw × fsw
Energy lost per transition × rate.
Effective Gate C
C = Qg / Vgs
Average capacitance driver sees.
Miller Plateau Time
tM = Qgd / Ig
Dominates Vds transition.

History of MOSFET Gate-Drive Design

Early power MOSFETs in the late 1970s were often driven by discrete op-amps or BJT totem-pole stages — adequate for kilohertz-range switching but inadequate for the higher frequencies needed to shrink inductors and capacitors. The first dedicated gate-driver ICs (Microchip TC4420, International Rectifier IR2110) appeared in the 1980s, integrating high-current complementary output stages, high-side level shifting, and dead-time control in a single package.

The \"Miller plateau\" phenomenon — a pause in the VGS rise during switching, caused by the Miller (Cgd) capacitance — was quantified by Brian Pelly in his seminal 1979 International Rectifier papers on MOSFET behavior. During the plateau, gate-drive current is consumed entirely by discharging Cgd against Vds\'s fall; longer plateau = slower switching = higher switching losses. Minimizing Qgd through cell-design optimization has driven MOSFET evolution ever since.

Modern gate drivers push into the tens of amps (UCC27714, LM5134) for driving large parallel FET banks at switching edges under 10 ns. GaN HEMT drivers (LMG1020, LM5045) specifically handle the smaller Qg and faster dv/dt of wide-bandgap devices. Isolated gate drivers (Si8261, FOD8332) use optical or magnetic coupling to safely drive high-side MOSFETs in kilovolt applications. The gate-drive formula in this calculator is the same one engineers have used since 1980 — only the driver silicon has gotten better.

About This Calculator

Enter total gate charge Qg (from datasheet, typically at the rated VGS), gate drive voltage, target switching time, switching frequency, and drain V/I conditions. The tool returns required peak gate current, maximum allowable gate resistor, switching loss estimate, and average drive power.

For the gate resistor: the computed value is a maximum. Reducing Rg gives faster switching and lower Psw, but risks EMI ringing and voltage overshoot. Practical Rg values are 1–22 Ω for low-side drivers, with additional series resistance in the high-side path when using bootstrap supplies. Always verify actual switching waveforms on an oscilloscope. All math runs client-side.

Frequently Asked Questions

What is gate charge?

Qg (total gate charge) is the charge needed to fully turn a MOSFET on, in nanocoulombs. Typical: 5-200 nC for logic-level FETs, 50-1000 nC for power FETs. Divide by drive voltage to get gate capacitance equivalent.

Why a gate resistor?

Limits peak current during switching, preventing damage to the gate driver. Also damps LC ringing from gate lead inductance + gate capacitance. Typical value: 5-50Ω. Smaller = faster switching but more ringing.

Switching loss matters?

At high frequency (>100 kHz), switching losses dominate over conduction (I²Rds). Total switching loss: P_sw = ½ × Vds × Id × (t_on + t_off) × f_sw. Faster switching = less loss.

Why does my FET run hot?

Common causes: (1) Rds(on) too high, (2) switching loss at high freq, (3) gate drive voltage too low (not fully enhancing), (4) body diode conduction. Check: hot at rest = conduction loss; hot only when switching = switching loss.

What drive voltage?

Logic-level FETs: 5V or 3.3V. Standard FETs: 10-12V for full enhancement (R_DS(on) rated). Avoid staying in the Miller plateau — ensure Vgs > Miller voltage for fast turn-on/off.

Common Use Cases

Motor Driver

H-bridge switching at 20 kHz. Qg = 50nC, drive V = 12V, t_sw target = 100ns. Peak gate current = 500mA.

Buck Converter Switch

500kHz buck with IRLR7843: Qg = 20nC, t_sw = 20ns. Peak I_gate = 1A — needs a proper gate driver IC.

Solid-State Relay

Slow switching (ms), low gate current. Small 100Ω resistor acceptable; no special driver needed.

Hot-Swap Controller

Inrush limiter at power-on. Slow gate turn-on (10-100 µs) limits capacitor charging current.

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