Pierce Crystal Oscillator Calculator
Design the load capacitors C1 and C2 for a Pierce crystal oscillator (the universal MCU crystal topology). Matches the crystal's specified load capacitance CL.
How to Use
- Enter crystal spec CL (load capacitance, from datasheet — typically 8, 12, 18 or 20 pF).
- Enter estimated stray capacitance Cs (PCB traces + pin loading, typically 5-7 pF).
- Tool computes matched C1 = C2.
Show Work
Formulas
History
George Washington Pierce, Harvard physicist, patented the Pierce oscillator in 1923. His design replaced the Hartley and Colpitts tuned-tank oscillators with a crystal acting as a series-resonant element between plate and grid of a vacuum tube, producing the most stable oscillator known at the time. Every quartz radio-transmitter oscillator from the 1930s to 1960s used this topology.
The CMOS-inverter Pierce configuration replaced tube versions in the 1970s as integrated-logic fabrication matured. The 74HC04 hex inverter chip was universally used to build MHz crystal oscillators for digital equipment — the same topology integrated today into every MCU\'s HSE oscillator pin pair (XIN/XOUT).
Modern Pierce circuits inside MCUs like STM32, ESP32, and AVR use an internal invertor + feedback resistor with external crystal + two caps. The caps set the load capacitance for tight frequency accuracy (typically ±10-20 ppm with good layout). Stray capacitance from PCB traces and ESD protection adds to the "effective" C1/C2, which is why datasheets often specify C1 = C2 = 2·(CL − 6 pF) rather than 2·CL.
About This Calculator
Enter crystal CL (from datasheet — 18 pF is common; 32.768 kHz watch crystals are typically 12.5 pF), estimated PCB stray capacitance (5-7 pF per pin for typical layouts), and crystal frequency. The tool solves C1 = C2 = 2·(CL − Cs) with equal caps assumption.
For frequency trimming, use trimmer cap on one side (3-20 pF). For precision, minimize PCB trace length, place ground plane directly under the crystal, and keep noisy digital traces away. Everything runs client-side.
Frequently Asked Questions
Why match CL?
A crystal oscillates at its specified frequency only when terminated in its nominal load capacitance CL. Under- or over-loading shifts the frequency by tens of ppm. For tight accuracy (watch, time stamping), match CL within ±0.5 pF.
Stray capacitance?
PCB pads, trace, IC pin loading — typically adds 3-7 pF to each crystal pin. Include in the CL match: CL_nominal = (C1·C2)/(C1+C2) + Cs. For 0.5 pF accuracy, minimize PCB trace length and keep ground plane directly under the crystal.
Drive level?
Crystals have a max drive spec (typically 100-300 µW). Add a series resistor R_d to reduce excess drive; 1-10 kΩ is typical for 32.768 kHz watch crystals, 470 Ω to 2.2 kΩ for MHz crystals.
Common Use Cases
MCU Clock Crystal
STM32 HSE: 8 MHz with CL=18 pF needs C1=C2≈24 pF (stray 6 pF).
RTC 32.768 kHz
CL=12.5 pF with 3 pF stray needs C1=C2=19 pF.
RF Reference
TCXO footprints use tight CL matching for ppm-level accuracy.
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