Serpentine Length-Match Calculator
Calculate serpentine trace geometry to match length between high-speed signals. Solves for number of loops, pitch, and added length.
How to Use
- Enter the length you need to add (mm).
- Enter straight-section length a and turn-amplitude b (how far the serpentine excursion goes).
- Enter trace width w and pitch spacing s (between serpentine turns).
- Tool returns the number of serpentine loops N needed, total footprint, and coupling factor.
Show Work
Formulas
History of Length Matching
Length matching entered mainstream PCB design with the 1998 release of Rambus RDRAM (600 MHz) and the 2000 release of PC133 SDRAM. Memory interfaces required data and strobe lines to arrive within a few hundred picoseconds of each other — distances that translated to millimeters of PCB trace. Serpentine delay sections became the standard solution, adopted immediately by Intel's motherboard designers and cascaded through the industry.
DDR, DDR2, DDR3, DDR4, and DDR5 have progressively tightened skew requirements from ±50 ps (DDR1) down to ±5 ps (DDR5), matching the shrinking cycle times. Modern ECAD tools (Altium Designer, Cadence Allegro, KiCad) include automatic length-tuning modes that generate serpentines to hit length targets within layout constraints.
The 3W rule (gap ≥ 3× trace width between adjacent signals) came from Motorola's 1990s signal-integrity best-practices guides and became the de-facto industry standard. Violating it causes visible self-crosstalk in the serpentine: TDR measurements show impedance dips at each turn where mutual coupling temporarily reduces the effective impedance.
About This Calculator
Enter the length that needs to be added (derived from your byte-lane timing target), plus serpentine geometry: excursion amplitude b, straight-section length a, trace width w, and pitch s. The tool computes the number of loops N = ceil(ΔL / 2b), total footprint size, and verifies the 3W gap rule.
For tight impedance control during length-matching, use the accordion or "snake" variants which minimize the number of 90° turns. For very tight matching (DDR5, PCIe Gen5, HDMI 2.1), consult your ECAD tool's built-in length-tuning function — it accounts for dielectric variation, fiber-weave effect, and trace-width tolerance that this first-pass tool can't. Everything runs client-side.
Frequently Asked Questions
Why length-match?
Parallel high-speed signals (DDR byte lanes, QSPI, SGMII, PCIe lanes) need to arrive at the receiver within a few picoseconds of each other. Different source-destination distances must be equalized with serpentine delay sections.
How close can turns be?
Rule of thumb: gap ≥ 3W to minimize self-crosstalk in the serpentine. Tighter coupling reduces effective added delay and causes impedance discontinuity at each turn.
Alternative topologies?
Accordion, trombone, zig-zag — different geometries trade off pitch vs. added length vs. impedance uniformity. Serpentine is the most compact for large length additions.
Common Use Cases
DDR4 Byte Lane Match
Pair all data bits in a byte lane to ±5 ps (±0.75mm on FR4).
PCIe Lane Match
Within-lane ±5 mils (±0.127 mm); inter-lane ±25 mils typical.
HDMI / DP
Intra-pair ±5 ps; inter-pair ±25 ps typical.
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