Signal Integrity Basics
High-speed digital design — reflections, crosstalk, power integrity, and termination.
Reference
When traces become transmission lines
- Rule of thumb
- Trace length > (t_r × 0.5) / (prop delay per unit)
- Example
- Signal with 1 ns rise time on FR-4 (~6 in/ns in outer): any trace > 3 in acts transmission-like
- Characteristic Z_0
- Depends on trace width, height above plane, dielectric. Common: 50 Ω single-ended, 100 Ω diff
Reflections
- Mismatch
- Γ = (Z_L − Z_0) / (Z_L + Z_0)
- Open end
- Γ = +1 (full reflection, doubles voltage)
- Short end
- Γ = −1 (full inversion)
- Termination
- End at Z_0 for no reflection. Can also source-terminate.
Termination styles
| Style | Where | Power | Use |
|---|---|---|---|
| Series | At source | Low | Point-to-point; DDR command lanes |
| Parallel | At far end | High | SSTL, LVDS (AC-coupled) |
| Thevenin | Split at far end | Medium | Bussed topology |
| AC | Cap + R at far end | Low | DDR4/5 differential |
| Differential | Across pair | Varies | USB, Ethernet, HDMI, MIPI |
Crosstalk
- Keep 3W spacing (3× trace width) between parallel traces.
- Avoid parallel runs > 10 mm on high-speed signals.
- Use guard traces or layer separation for critical signals.
- Break 90° turns into two 45° segments or arcs.
Power integrity
- Provide tight decoupling — cap close to IC power pins, continuous ground return.
- Avoid split planes under high-speed signals — return currents are forced to detour.
- Use bulk cap (10 µF) near regulators, distributed ceramics (100 nF) at ICs.
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