Digital Timing Basics

Key times

t_setup

Data must be stable BEFORE clock edge

t_hold

Data must remain stable AFTER clock edge

t_co / t_cq

Clock-to-Q propagation delay

t_comb

Combinational logic delay between flip-flops

t_skew

Clock arrival difference between two endpoints

t_jitter

Short-term variation in clock edge timing

Max clock frequency

Setup constraint

T_clk ≥ t_co + t_comb + t_setup + t_skew + t_jitter

Hold constraint

t_co + t_comb_min ≥ t_hold + t_skew

Max f_clk

= 1 / T_clk_min

Metastability

• Occurs when data transitions during the setup/hold window — flip-flop output may stay in undefined region.
• Synchronize async signals with a 2-flop (or 3-flop for high-speed) synchronizer before use.
• MTBF (mean time between failures) falls exponentially with extra flip-flop stage time.
• Never fan out an async signal to multiple downstream flops — they may sample differently.

Clock domain crossing

• Single-bit: 2-flop synchronizer.
• Multi-bit: handshake (req / ack) or async FIFO.
• Gray-coded counters for pointer CDC — only one bit changes per step.
• Never assume flags transfer atomically across clock domains.