PCB Stackup Impedance Planner

Multi-layer PCBs entered production in the early 1960s for US military aerospace applications — the Minuteman II guidance computer used 10-layer PCBs in 1964. Commercial 4-layer boards arrived in the 1980s as digital logic clocks exceeded 1 MHz and required dedicated ground-plane returns. By the 2000s, 6-8 layer HDI boards became standard in laptops, smartphones, and routers.

The "signal / ground / power / signal" 4-layer stackup became the industry baseline in the 1990s — outer signal layers reference the adjacent ground or power plane, giving controlled impedance. More advanced stackups (6/8/10+ layers) add dedicated stripline routing between ground planes for the tightest signal-integrity requirements.

Modern HDI stackups push impedance control to extremes: smartphone mainboards use 10-16 layer stackups with laser-drilled microvias (0.1 mm diameter), allowing signal routing between 0.05 mm-pitch BGA pads. PCIe Gen5 and DDR5 require controlled impedance to ±5% — achievable only with prepreg thickness tolerances of ±5 µm, verified with coupon TDR on every production panel.

Pick layer count (4/6/8), total board thickness, copper weight, and εr. The tool computes symmetric dielectric distribution and proposes trace widths for 50Ω single-ended and 100Ω differential on both outer and inner signal layers, using the Hammerstad-Jensen (microstrip) and Cohn-Wadell (stripline) closed-form equations.

This is a first-pass planner. For production, your PCB fabrication house will issue a specific stackup drawing based on their available materials and process tolerances. They'll also produce impedance-verified stackup documents (TDR coupons) for controlled-impedance fabs. Everything runs client-side.