Stripline Trace Impedance Calculator

Calculate characteristic impedance Z₀ of a stripline (embedded) trace sandwiched between two ground planes. Centered and offset variants.

Calculator Electronics Updated Apr 23, 2026
How to Use
  1. Enter trace width W, total substrate height B (between the two ground planes), trace thickness T.
  2. Enter dielectric constant εr of the entire substrate.
  3. Result: Z₀ assuming centered trace. Use offset formula if trace is off-center.
Input
mm
mm
mm
Presets
Cross Section
Z₀
Ω
W/(B−T)
Prop. Delay
ps/mm
vs Microstrip

Show Work

Enter dimensions.

Formulas (IPC-2141 / Cohn)

Z₀ (centered)
60/√εr · ln(4B / (0.67π(0.8w + t)))
Wadell closed form.
Propagation Delay
tpd = √εr / c
Pure substrate, no fringing.
50Ω Rule (FR4)
w ≈ 0.2 × B
Centered stripline, 1oz Cu.
Advantage
Loss ~70% of microstrip
No radiation, no fringing.
Disadvantage
Harder to probe
Buried trace, no TDR access.
Validity
w/(B−t) < 0.35, t/B < 0.25
Accuracy ±1%.

History of Stripline

Robert Barrett at the Air Force Cambridge Research Laboratories developed stripline in 1952 under Seymour Cohn's group as a miniature microwave transmission line. Cohn's 1955 analysis derived the closed-form Z₀ equations still used today. Stripline enabled compact radar-system microwave circuitry in the Cold War era — filters, couplers, and matched amplifiers an order of magnitude smaller than their waveguide equivalents.

The stripline's "TEM mode" propagation (pure transverse electromagnetic, no longitudinal field component) is its key advantage: signals travel at a single velocity set by √εr, with no dispersion and no radiation loss. This made it the preferred technology for precision microwave passive components until surface-mount ceramic and LTCC processes caught up in the 1990s.

Modern PCB stackups on 4+ layer boards use stripline for inner-layer controlled-impedance routing — DDR4/5, PCIe Gen4+, USB4, and all high-speed digital traces above ~1 GHz benefit from stripline's lower radiated emissions and higher isolation vs. microstrip on outer layers.

About This Calculator

Enter width W, full plane-to-plane spacing B, copper thickness T, and substrate dielectric constant εr. The tool assumes centered stripline (equal dielectric above and below) using the IPC-2141 / Cohn-Wadell closed-form equation.

For offset stripline (trace closer to one plane than the other), Z₀ drops — use a field solver or the asymmetric stripline formulas. Comparison readout shows approximate microstrip Z₀ for the same geometry so you can see the ~10-15% difference. Everything runs client-side.

Frequently Asked Questions

Stripline vs microstrip?

Stripline has ground planes above AND below — better EMI shielding, constant εr throughout, but harder to inspect/probe and requires inner-layer routing.

Why lower loss?

Fields are fully contained in the substrate. No fringing to air, no radiation. Typical stripline has ~30% less loss than equivalent microstrip at GHz frequencies.

Centered vs offset?

Centered: midway between top and bottom ground. Offset (asymmetric stripline): closer to one ground. Offset has lower Z₀ for same W, higher crosstalk rejection.

Common Use Cases

RF Backplane

Inner-layer 50Ω lines in multi-GHz backplanes and server motherboards.

PCIe Gen4/5

85-100Ω diff stripline on inner layers for controlled-impedance PCIe routing.

High-Speed Clock

Stripline rejection of external EMI for low-jitter clock distribution.

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