Phase Noise → Jitter Calculator

Convert phase noise (dBc/Hz at offset) to RMS timing jitter (ps) for clock oscillators. Integrate single-point or multi-point phase-noise specs.

Calculator Electronics Updated Apr 23, 2026
How to Use
  1. Enter carrier frequency and phase noise at a single offset (or use a flat-band approximation).
  2. Enter the integration bandwidth (f_low to f_high).
  3. Tool computes RMS integrated phase noise and converts to timing jitter in ps.
Input
Hz (MHz, GHz OK)
dBc/Hz (flat-band)
Hz (kHz, MHz OK)
Hz (kHz, MHz OK)
Presets
Phase Noise Plot
RMS Jitter
ps
RMS Phase
rad
BW
Integ. Noise
dBc

Show Work

Enter parameters.

Formulas

Integrated phase
σ²_φ = 2·∫ L(f) df
L(f) = linear dBc/Hz ratio.
Flat-band approx
σ²_φ ≈ 2·L·(f_hi − f_lo)
When PN is roughly flat.
Jitter from φ
σ_t = σ_φ / (2π·f₀)
Time equivalent.
Combined
σ_t = √(2·L·BW) / (2π·f₀)
Simplified single-step.
1/f region
L(f) ∝ 1/f³ below corner
Flicker dominates low-offset.
Target specs
< 1 ps: 10GbE; < 100 fs: 5G
Modern clock jitter targets.

History of Phase Noise Analysis

David Leeson\'s 1966 Proc. IEEE paper, "A simple model of feedback oscillator noise spectrum," established the classical phase-noise model still used today. Leeson showed that an oscillator\'s phase noise spectrum has a characteristic 1/f² slope near the carrier and a flat noise floor at large offsets — governed by the resonator Q, feedback gain, and device flicker noise.

The phase-noise-to-jitter conversion (σ_t = σ_φ / 2πf₀) became critical in the 1990s as high-speed digital-communication systems pushed into the GHz range. An OC-192 SONET link at 10 Gbit/s requires < 1 ps RMS jitter integrated over 12 kHz to 20 MHz — a spec that demands ultra-low phase noise in the reference clock.

Modern 5G and coherent-optical receivers require sub-100 fs jitter, achievable only with high-Q SAW or MEMS oscillators (Q > 50,000) or with optical frequency combs. The mathematical relationship between phase noise and jitter hasn\'t changed in 60 years; only the numerical targets keep getting tighter.

About This Calculator

Enter carrier frequency f₀, flat-band phase noise L(f) in dBc/Hz, and your integration bandwidth (f_low to f_high). The tool computes RMS integrated phase σ_φ = √(2·L·BW) and converts to jitter σ_t = σ_φ / (2π·f₀).

This uses a flat-band approximation — if your phase-noise spec varies with offset (typical shape: slope of −30 dB/decade near carrier, flattening at large offsets), you need to integrate the L(f) curve piecewise. For first-pass design, this single-number approximation is within a factor of 2× for most real oscillators. Everything runs client-side.

Frequently Asked Questions

What is phase noise?

Random short-term frequency variations in an oscillator, expressed as single-sideband noise power relative to the carrier (dBc/Hz) at offset frequencies. Key spec for clock sources.

Jitter vs phase noise?

Same phenomenon in different units. Phase noise = frequency-domain, dBc/Hz at each offset. Jitter = time-domain, RMS picoseconds integrated over some bandwidth.

Integration bandwidth?

Depends on application. For 10GbE clock (156.25 MHz), integrate 12 kHz to 20 MHz. For SDR LO, 1 kHz to 100 MHz. Always specify BW when quoting jitter.

Common Use Cases

10 GbE Reference

Typical target: &lt; 1 ps RMS jitter (12 kHz to 20 MHz).

5G Radio

&lt; 100 fs RMS jitter; achievable with crystal oscillators with ultra-low phase noise.

ADC Clock

12-bit ADC at 1 GSPS: needs &lt; 1 ps RMS to preserve SNR.

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