PLL Loop Filter Calculator
Design a 2nd or 3rd-order passive loop filter for a charge-pump PLL. Solves R and C values from loop bandwidth, phase margin, charge-pump current, and VCO gain.
How to Use
- Enter charge-pump current Kφ (A/rad), VCO gain Kv (Hz/V), divider N, and target loop BW + phase margin.
- Tool computes R2, C1, C2 for a 2nd-order passive filter (3 components).
Show Work
Formulas (2nd-order passive)
History
The phase-locked loop concept dates to Henri de Bellescize\'s 1932 paper on synchronous reception of AM radio, but charge-pump PLLs for frequency synthesis emerged in the 1970s with Fairchild\'s 4046 CMOS PLL IC and Motorola\'s MC145xxx PLL-synthesizer family. These chips needed external passive loop filters to smooth the charge-pump output into a clean VCO control voltage.
The loop-filter design equations for 2nd/3rd/4th-order passive filters were codified in the 1980s by Dean Banerjee at National Semiconductor. His 1997 app note AN-1001 "PLL Performance, Simulation, and Design" became the industry bible — every modern PLL synthesizer datasheet references these equations.
Modern integrated PLL synthesizers (TI LMX2594, ADI ADF4356) include digitally-controlled loop filter tuning, but discrete external RC loop filters are still universal for cost-sensitive designs, RF prototype boards, and any application requiring the lowest close-in phase noise achievable from a given VCO.
About This Calculator
Enter charge-pump current Kφ (amp per 2π radians phase error — typical 1-10 mA), VCO gain Kv (frequency change per volt — typical 10-100 MHz/V), divider N (RF frequency / reference frequency), and desired loop bandwidth + phase margin. The tool solves for the standard 2nd-order passive loop filter components (C1 across the VCO input, R2+C2 in series across C1).
For 3rd-order (low spur) filters, add R3+C3 in series from the VCO node to ground — this calculator computes the 2nd-order core; R3, C3 add a far-out pole computed separately. Verify simulation with ADIsimPLL or TI\'s PLLatinum SimSE before committing to PCB. Everything runs client-side.
Frequently Asked Questions
Loop bandwidth?
PLL bandwidth trade-off: fast lock vs phase-noise suppression. Typical f_BW = f_ref / 10. For a 1 MHz reference, 100 kHz loop BW. Lower BW = cleaner VCO phase noise, slower lock time.
Phase margin?
45-60° typical. Below 30°: peaking, overshoot on frequency jumps. Above 70°: slow, overdamped lock. 45° is the industry-standard compromise.
3rd order?
Add C3 across R2 to make the filter 3rd-order — adds a far-out pole that suppresses reference-frequency spurs at the VCO. Required for low-jitter designs.
Common Use Cases
Clock Synth
Si5351, CDCE913: integer-N PLL for digital clock distribution.
Cellular LO
Fractional-N synthesizer for LTE carriers, 10 kHz loop BW typical.
FM Deviation
Narrow-BW PLL to enforce FM-deviation spec without corrupting audio.
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