Propagation Delay Calculator

Propagation delay became an active engineering concern with the rise of ECL (emitter-coupled logic) in the 1970s and BiCMOS/ECL hybrid designs in the 1980s, where clock edges could resolve in a few hundred picoseconds. Classic TTL designs at tens of MHz could ignore PCB trace delay; ECL at 300–500 MHz couldn\'t. Cray\'s mainframes of the 1970s–80s famously used equal-length twisted-pair wire-wrap interconnect specifically to match propagation delays across a multi-board system.

Modern high-speed digital interfaces — DDR4 at 3200 MT/s, PCIe Gen4/5/6, USB 3.2/4, Ethernet 25G/100G — all specify tight length-matching across parallel data lanes. A 1-inch length mismatch on FR-4 is ~140 ps, more than enough to push a DDR4 byte lane out of its data-valid window. Tight matching requires serpentine routing (trombones) and length-tuning in the PCB design tool, followed by time-domain verification on a real board.

Dielectric-loss considerations at high frequencies changed material selection. Standard FR-4 works fine through ~3 GHz but attenuates signals heavily above 5 GHz; specialty materials (Rogers 4350B, 4003, Isola I-Tera) with lower loss tangent and more controlled ε_r extend usable bandwidth. Modern servers and 5G radios routinely use these premium materials despite their cost because signal integrity at multi-GHz demands it.

Enter trace length (with mm/cm/m/in suffixes), effective dielectric constant (or pick a common medium from the dropdown). The tool computes propagation delay, delay per mm/inch, signal velocity as a fraction of c, and velocity factor.

For microstrip on FR-4, use ε_r,eff ≈ 3.1; for stripline, use the full ε_r ≈ 4.3 (stripline traces are buried between ground planes, fully surrounded by dielectric). For coax and other transmission lines, the velocity factor preset captures the right physics. For DDR and high-speed interfaces, compare your results against the datasheet\'s timing budget. All math runs client-side.