Setup / Hold Timing Calculator

Evaluate setup and hold margin for a synchronous flip-flop.

Calculator Electronics Updated Apr 18, 2026
How to Use
  1. Enter clock period, tCO, tData, tSU, tH, skew.
  2. Setup margin = T − tCO − tData − tSU + skew.
Input
Presets
Timing
Setup margin
Hold margin
Max fclk
Status

Show Work

Enter values to see the timing margin calculation.

Formulas

Setup Margin
T − tCO − tDat − tSU + skew ≥ 0
Data path must settle before next edge.
Hold Margin
tCO + tDat − tH − skew ≥ 0
Data must stay stable after edge.
Max Clock Frequency
fmax = 1 / (tCO + tDat + tSU − skew)
Limit imposed by longest path.
Positive Skew
Helps setup, hurts hold
Destination clock arrives later.
Negative Skew
Helps hold, hurts setup
Destination clock arrives earlier.
Metastability MTBF
e(tr/τ) / (fclk·fdata·τ)
Rises exponentially with resolution time.

History of Setup/Hold Timing Analysis

The concepts of setup time (tSU) and hold time (tH) emerged from flip-flop datasheets in the late 1960s as TTL logic became fast enough that timing violations became practical concerns. Phil Chapnick\'s 1973 paper "Anomalous behavior of synchronizer and arbiter circuits" gave the first rigorous treatment of metastability — what happens when setup/hold times are violated and the flip-flop enters an indeterminate state.

Static Timing Analysis (STA) as a formal methodology was developed at IBM in the late 1970s by R. Hitchcock, G. Smith, and D. Cheng. Their algorithms propagated earliest-arrival and latest-arrival times through combinational logic and flagged any register-to-register path where tCO + tDat + tSU exceeded the clock period. This became the standard timing closure methodology for custom ASICs and later FPGAs; every modern synthesis tool (Synopsys Design Compiler, Cadence Genus, Xilinx Vivado) runs exhaustive STA as part of the build flow.

Clock skew — the difference in clock arrival times between source and destination flip-flops — was originally a bug to minimize, but it turned out to be usefully manipulable. "Clock skew scheduling" techniques deliberately introduce calculated skew to balance setup and hold margins on critical paths, effectively time-borrowing between pipeline stages. Modern high-performance CPUs exploit this aggressively.

About This Calculator

Enter clock period T, clock-to-output delay tCO, combinational data path delay tDat, destination register setup/hold times tSU/tH, and clock skew. The tool computes setup margin, hold margin, maximum achievable clock frequency, and pass/fail status.

Positive margins = safe design; negative margins = timing violation that will cause metastability or outright functional failure. For mission-critical designs, add 10–20% margin to cover PVT (process, voltage, temperature) variation — the datasheet values are nominal, and corner-case silicon at worst-case voltage and hottest operating temperature can add 20–30% to all delays. All math runs client-side.

Frequently Asked Questions

Metastability?

Setup or hold violation can cause latching to indeterminate state.

Skew sign?

Positive if destination clock arrives later than source.

Common Use Cases

FPGA STA

Validate timing closure.

Discrete Logic

High-speed CPLD.

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