PWM → Voltage Calculator

Before dedicated DAC ICs became cheap in the mid-1980s, designers routinely used PWM-plus-RC-filter as a low-cost voltage-output DAC. The technique appeared in analog synthesizers of the 1970s (control voltage generation from digital sequencers), in early industrial controllers (Eurotherm's digital temperature controllers drove analog thyristor gates via PWM), and throughout the Apple II / BBC Micro ecosystems where a single GPIO and two passive components became an analog output.

The key trade-off is always the same: higher PWM frequency lowers ripple, but MCU timer resolution limits how fine the duty cycle can be at high frequencies. An 8-bit PWM at 100 kHz has only 10 ns per LSB, limiting you to a 16-MHz timer clock ceiling. 10-bit PWM needs ~40 ns per step, 12-bit needs ~160 ns. Most modern MCUs include dedicated PWM peripherals with 10-16 bit resolution and MHz-range operation via timer clock scaling.

For audio-grade performance, oversampled PWM (class-D amplifiers) uses feedback to shape the noise spectrum so ripple falls out-of-band. Single-chip Class-D amps like the TPA3116 implement full PWM + LC filter + feedback in a TSSOP package, delivering 50 W at 90% efficiency from a 24 V supply.

Enter Vcc (PWM high level), duty cycle (0-1), PWM frequency, and filter R and C. The tool returns average output voltage Vcc × D (the DC component), peak-to-peak ripple Vcc·D·(1-D)·T/(RC) (small-ripple approximation, valid when ripple < 5% of Vavg), RC time constant, and filter corner frequency 1/(2πRC).

Rule of thumb: place the RC corner 10-100× below the PWM frequency so the filter achieves 20-40 dB attenuation at the fundamental. Worst-case ripple is at 50% duty. For higher-quality DACs, cascade two RC sections (second-order rolls off 40 dB/decade) or add an op-amp buffer to isolate the filter from load. Everything runs client-side; no values leave your browser.