Switch-Mode Power Supply (SMPS) Efficiency Calculator
Compute overall efficiency of a switch-mode DC-DC converter by summing loss contributions from the MOSFET (conduction + switching), diode (forward drop + reverse recovery), inductor (DCR + core), output capacitor ESR, and controller IC bias current.
How to Use
- Enter the output power P<sub>out</sub> in watts.
- Enter estimated losses for each category: FET (conduction + switching), diode (forward drop + reverse recovery), inductor (DCR + core), cap ESR, and control IC bias.
- The calculator sums losses, adds them to P<sub>out</sub> to get input power, and reports efficiency η = P<sub>out</sub> / P<sub>in</sub>.
- The breakdown identifies the dominant loss contributor — where to focus design optimization.
Show Work
Formulas
History of SMPS Efficiency Engineering
Switch-mode power supplies trace to 1950s radar and early computer applications where high-efficiency conversion of 400 V to logic levels was essential. The first commercial SMPS for computers appeared in the late 1960s; IBM\'s System/360 mainframes pioneered line-operated switchers at scale. Early converters ran at 20 kHz (just above audible range) and achieved 70–80% efficiency.
The transition from linear to switching supplies accelerated through the 1970s–80s as cheap fast-switching bipolar and later MOSFET transistors became available. Ed Abramson and Bob Mammano\'s 1976 paper on PWM control established the design methodology; Bob Erickson and Dragan Maksimović\'s Fundamentals of Power Electronics (1999) became the definitive engineering textbook. Loss accounting — the kind this calculator does — has been standard practice since the 1970s.
Modern efficiency gains come from: synchronous rectification (replacing diodes with MOSFETs), GaN and SiC wide-bandgap semiconductors (lower switching losses), digital control loops (dynamic optimization), and active dead-time tuning. State-of-the-art converters now reach 98–99% at specific operating points — losses are approaching fundamental physical limits, and further improvements require entire topology changes (e.g., soft-switching LLC resonant converters instead of hard-switched buck/boost).
About This Calculator
Enter output power and the six main loss categories. The tool computes total loss, input power, efficiency percentage, and identifies the dominant loss contributor — pointing you to where design optimization would pay off most.
For estimated values, use these starting points: FET 1–3% of Pout, diode 1–2% (higher for non-synchronous), inductor 1–2%, cap ESR 0.3–0.8%, control bias 0.1–0.5%. Refine with datasheet specs and simulation for precise numbers. Everything runs client-side.
Frequently Asked Questions
Where do SMPS losses come from?
Five main categories: (1) MOSFET conduction loss I²·R<sub>DS(on)</sub>·D; (2) MOSFET switching loss (gate drive + overlap losses ~ V·I·t<sub>sw</sub>·f<sub>sw</sub>); (3) diode losses V<sub>f</sub>·I·(1−D) plus reverse-recovery charge Q<sub>rr</sub>·V<sub>r</sub>·f; (4) inductor losses I<sub>rms</sub>²·DCR plus core hysteresis/eddy; (5) capacitor ESR I<sub>rms</sub>²·R<sub>ESR</sub>. Adding them gives total loss.
Why does light-load efficiency drop?
Fixed losses — controller IC bias current, gate-drive power, core loss — don\'t scale down with output power. At P<sub>out</sub> = 1 W with 200 mW of fixed loss, η drops below 85% even with zero conduction loss. PFM (pulse-frequency modulation) and skip modes turn off switching between pulses to cut fixed loss at light load, raising standby efficiency dramatically.
What is 80 Plus?
A voluntary PC power supply efficiency certification program started in 2004. Basic 80 Plus requires ≥80% efficiency at 20%, 50%, and 100% load; tiers go up through Bronze, Silver, Gold, Platinum, and Titanium (≥94% at 50% load, ≥90% at 10% load). Each step costs more; Titanium is reserved for servers and enthusiast PCs.
Does efficiency vary with load?
Yes. Typical η curve: rises sharply from 0 to ~30% load, plateaus at 50–80% load (peak efficiency), drops slightly above 80% (conduction losses dominate). Design goal: make peak η fall at typical operating load, not nameplate full load.
What's the difference between synchronous and non-synchronous topologies?
Non-synchronous: passive diode for freewheeling current; diode drops V<sub>f</sub> (~0.4 V Schottky) every off-cycle. Synchronous: active MOSFET replaces the diode; drop is I·R<sub>DS(on)</sub>, often well below V<sub>f</sub>. Synchronous boosts efficiency 2–5% at high currents but adds cost and complexity (gate drive, dead-time control).
Common Use Cases
Buck Converter Loss Budget
Typical 5 V, 3 A buck at 500 kHz: ~0.3 W FET conduction, 0.15 W switching, 0.2 W synchronous MOSFET, 0.1 W inductor DCR, 0.05 W cap ESR = 0.8 W total loss, ~95% efficiency.
Flyback PSU Analysis
Universal-input 100 W flyback: primary FET ~2 W, secondary diode ~2 W (Schottky), transformer ~1.5 W, cap ESR ~0.5 W = ~6 W loss, ~94% efficiency. Reality is 80–88% due to higher switching-edge losses.
High-Frequency GaN Buck
GaN FETs enable 1–6 MHz switching with minimal switching losses. At 5 MHz, a 100 W GaN buck can hit 96%+ efficiency — impossible with silicon MOSFETs at the same frequency.
Data-Center 48 V to POL
Rack-level 48 V distribution feeds point-of-load regulators at CPU/GPU sockets. 48 V → 1 V conversion at 200+ A uses multi-phase interleaved bucks with 97–98% efficiency — essential for data-center energy economics.
Laptop Charger Specification
65 W USB-C PD charger typically rated at 91–93% peak efficiency. Standby losses must stay below 75 mW per DoE / EPS v2 regulations — drives micropower control IC design.
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