PCB Via Inductance Calculator

The formula for inductance of a straight cylindrical conductor was derived by Edward Bennett Rosa at the US Bureau of Standards in 1908 as part of the bureau's comprehensive study of self- and mutual-inductance of conductors. Rosa's formulas remain the closed-form reference for round-wire and via inductance calculations more than a century later.

PCB via inductance became a first-class signal-integrity concern in the 1990s when CPU and memory interface speeds pushed past 100 MHz. Suddenly the 1-2 nH parasitic inductance of a standard through-hole via created a measurable impedance discontinuity at the vias' self-resonant frequency (typically 1-3 GHz). Modern HDI (high-density interconnect) PCBs use microvias (blind, buried, stacked) to reduce via inductance by 5-10× for high-speed interfaces.

Power-delivery networks (PDNs) rely on many parallel vias to reduce effective L at decoupling capacitors. A single 1 nH via at 1 A/ns load-step produces a 1 V drop on the power rail — unacceptable for 1.0 V core voltages. Ten parallel vias drop that to 100 mV. Modern VRMs use hundreds of via-pairs between output stage and BGA mounting pads to meet PDN impedance targets down to 1 mΩ at 100 MHz.

Enter via length (stackup depth it traverses), drill radius, and number of parallel vias. Optional: frequency for Z-magnitude readout, di/dt for voltage-drop estimate. The formula is the cylinder-wire approximation from Rosa 1908 — accurate to ~10% for typical PCB via aspect ratios.

For more accurate modeling (especially at multi-GHz frequencies where via stub resonances dominate), use a 3D field solver (Ansys HFSS, CST). For power-delivery PDN design, parallel via count and return-via proximity matter more than the single-via number computed here. Everything runs client-side.