PCB Via Inductance Calculator
Calculate parasitic inductance and self-resonant frequency of a PCB via. Estimates voltage drop at high-current transients.
How to Use
- Enter via length L (stackup depth between layers the via connects).
- Enter via drill radius r (typical 0.1-0.25 mm).
- Tool computes self-inductance, impedance at given frequency, and voltage drop at given di/dt.
Show Work
Formulas
History of Via Modeling
The formula for inductance of a straight cylindrical conductor was derived by Edward Bennett Rosa at the US Bureau of Standards in 1908 as part of the bureau's comprehensive study of self- and mutual-inductance of conductors. Rosa's formulas remain the closed-form reference for round-wire and via inductance calculations more than a century later.
PCB via inductance became a first-class signal-integrity concern in the 1990s when CPU and memory interface speeds pushed past 100 MHz. Suddenly the 1-2 nH parasitic inductance of a standard through-hole via created a measurable impedance discontinuity at the vias' self-resonant frequency (typically 1-3 GHz). Modern HDI (high-density interconnect) PCBs use microvias (blind, buried, stacked) to reduce via inductance by 5-10× for high-speed interfaces.
Power-delivery networks (PDNs) rely on many parallel vias to reduce effective L at decoupling capacitors. A single 1 nH via at 1 A/ns load-step produces a 1 V drop on the power rail — unacceptable for 1.0 V core voltages. Ten parallel vias drop that to 100 mV. Modern VRMs use hundreds of via-pairs between output stage and BGA mounting pads to meet PDN impedance targets down to 1 mΩ at 100 MHz.
About This Calculator
Enter via length (stackup depth it traverses), drill radius, and number of parallel vias. Optional: frequency for Z-magnitude readout, di/dt for voltage-drop estimate. The formula is the cylinder-wire approximation from Rosa 1908 — accurate to ~10% for typical PCB via aspect ratios.
For more accurate modeling (especially at multi-GHz frequencies where via stub resonances dominate), use a 3D field solver (Ansys HFSS, CST). For power-delivery PDN design, parallel via count and return-via proximity matter more than the single-via number computed here. Everything runs client-side.
Frequently Asked Questions
Why care about via L?
At high frequencies, via inductance becomes the dominant impedance — not via resistance. A 1 nH via has +j6.3 Ω at 1 GHz. Multi-GHz signals routed through vias see significant impedance discontinuities unless the via is kept short and well-referenced.
How to reduce?
(1) Shorter vias (blind/buried/microvias). (2) Multiple parallel vias (L ∝ 1/N, not 1/N exactly due to mutual coupling). (3) Return vias within 1mm of the signal via.
Signal via vs power via?
Signal vias carry high-frequency edges — inductance matters. Power/ground vias carry DC + switching noise — resistance matters more for DC drop, inductance still matters for switching transients.
Common Use Cases
Decoupling Cap Via
Bulk cap mounting pads to power plane: each mounting via adds ~1 nH. Parallel multiple vias to reduce effective inductance.
High-Speed Signal
PCIe Gen4 (16 GT/s) through 1.6mm FR4 via: ~1.2 nH = ~12 Ω at 1.6 GHz. Significant reflections without careful stackup.
Power Delivery
VRM output to CPU package: many parallel vias minimize L × di/dt voltage droop during load steps.
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