PCB Thermal Via Array Calculator

The thermal via array technique dates to the 1980s as surface-mount QFN/DFN packages started replacing through-hole TO-220 and TO-252 parts. Without the TO-220's heat-sinkable tab, power components needed an alternative thermal path — arrays of copper-plated vias under the exposed thermal pad became the standard solution, documented in TI and National Semiconductor application notes by the mid-1990s.

The AMP/Molex "standard" QFN thermal-pad pattern is a 3×3 or 5×5 grid with 1.0 mm pitch and 0.3 mm drill diameter. Each via provides roughly 40-60°C/W thermal resistance; 9 in parallel gives ~5°C/W, adequate for 5-10 W dissipation with reasonable ambient-to-copper-plane ΔT budgets.

Copper-filled microvia technology, introduced in smartphone mainboards after 2010, brought thermal via performance to a new level: ~10°C/W per via with 0.1 mm diameter. High-power RF PA modules in 5G base stations now use copper-coin inlay or embedded-component PCBs for thermal paths well beyond what via arrays alone can achieve.

Enter via length (stackup depth), drill radius, copper plating thickness, and number of parallel vias. Toggle filled/unfilled. The tool computes single-via thermal resistance (using copper k = 400 W/m·K on the plating-tube annulus), divides by N for the parallel array, and reports the max power for a typical 40°C rise budget.

This is the "via array only" thermal resistance — it doesn't include the PCB copper plane spreading resistance (which adds ~5-20°C/W for typical 40mm² pours) or external convection. For accurate thermal analysis of complete packages, use a dedicated thermal simulator (FloTherm, 6SigmaET, Icepak). Everything runs client-side.