CMOS Inverter Delay Calculator
Calculate switching time, propagation delay, and power dissipation for a CMOS inverter driving a capacitive load.
How to Use
- Enter supply voltage, load capacitance, and transistor on-resistance.
- Tool estimates propagation delay and dynamic power.
- Use to estimate fan-out delay in digital logic.
Show Work
Formulas
History of the CMOS Inverter
Frank Wanlass invented the CMOS inverter at Fairchild Semiconductor in 1963, pairing an N-channel and P-channel MOSFET in a complementary configuration. His key insight: only one transistor conducts at a time in steady state, so the static current is essentially zero — just leakage. Dynamic power (charging and discharging capacitance) dominates instead, which is why CMOS became the foundation of every low-power digital IC from the 1970s onward.
The classic delay formula tp = 0.69·R_on·CL comes from first-order RC analysis: the inverter's pull-up or pull-down transistor acts as a resistor driving the load capacitance, and 0.69 = ln(2) is the time to reach the 50% crossing point. In practice, R_on varies with gate-source voltage (hence saturation and triode regions), and more accurate α-power-law models (Sakurai 1990) are used in modern EDA tools.
Dennard scaling (1974) predicted that as MOSFETs shrink, gate capacitance shrinks proportionally while speed increases — enabling Moore's Law's doubling cadence through the 1990s. Dennard scaling broke down around 2005 when leakage currents (sub-threshold, gate-oxide tunneling) stopped shrinking, forcing the industry to multi-core architectures and FinFET transistors. But the fundamental tp = 0.69·Ron·CL relationship still governs every internal logic cell in a modern SoC.
About This Calculator
Enter supply voltage Vdd, load capacitance CL, transistor on-resistance R_on, and switching frequency. The tool returns propagation delay tp = 0.69·R_on·CL (50% to 50%), 10-90% rise/fall time 2.2·R_on·CL, dynamic power P = CL·Vdd²·f (the classic CMOS dynamic-power formula), and a rough maximum frequency estimate.
Note: this is an idealized single-stage analysis. Real chip power includes short-circuit current (during transitions when both transistors conduct briefly), leakage current (which dominates at > 45 nm process nodes), and clock-tree distribution power. For full SoC power analysis, use EDA tools like Synopsys PrimePower or Cadence Voltus. Everything runs client-side; no values leave your browser.
About the CMOS Inverter Delay Calculator
Working on electronics and circuit design? The CMOS Inverter Delay Calculator is a free browser tool that gives you the answer in seconds. Calculate switching time, propagation delay, and power dissipation for a CMOS inverter driving a capacitive load.
How it works
Put each value in its box and read the answer as you go. Because it recalculates live, you can play with the inputs to see how each one moves the result — handy for checking your own working or planning ahead. Everything happens on your device, so it is fast and private.
Want the deeper story? The Knowledge Base explains the ideas behind the tools in more detail.
Frequently Asked Questions
What sets delay?
RC time constant of on-resistance × load capacitance. Propagation delay = 0.69 × Ron × CL — the 50% crossing point.
Dynamic power?
P = CL × Vdd² × f (each transition charges/discharges CL through supply). Frequency × capacitance × voltage squared.
How do I use the CMOS Inverter Delay Calculator?
Simply type your numbers and read the result, which refreshes the instant you change something. There is nothing to submit and nothing to wait for.
Do I need to install or sign up for anything?
Not at all — it runs in the browser with nothing to install and no account. After it loads once, it even works without an internet connection.
Is my information private?
Yes. Everything happens in your browser. Nothing you type is sent to a server or saved anywhere.
Common Use Cases
Clock Tree
Buffer chain sizing to drive fan-out while meeting timing.
I/O Driver
Output buffer sizing for external capacitive loads.
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