SPI Timing Budget Calculator

Compute SPI timing budget: setup, hold, propagation delay, trace delay, and driver/receiver spec to verify valid operation at target clock.

Calculator Electronics Updated Apr 23, 2026
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How to Use
  1. Enter SPI clock, driver output delay (tCO), receiver setup/hold spec (ts, th).
  2. Enter PCB trace delay (1-6 ps/mm typical).
  3. Tool verifies worst-case margin.
Input
Hz (MHz OK)
ns
ns
ns
mm
Presets
Timing Diagram
Clock Period
—ns
Setup Margin
—ns
Hold Margin
—ns
Verdict
—

Show Work

Enter values.

Formulas

Clock period
T = 1 / f_SCK
Full period.
Half period
T/2
Time between edges for sample.
Trace delay
6.5 ps/mm FR4 inner
Microstrip ~6 ps/mm.
Setup margin
T/2 − tCO − t_trace − t_setup
Positive = OK.
Hold margin
tCO + t_trace − t_hold
Positive = OK.
Fix
Reduce f_SCK or use DDR
If margin negative.

History of SPI

Motorola introduced SPI in the late 1970s for Motorola MC68xx microcontroller peripheral interconnect. Unlike I2C, SPI prioritizes speed over pin count - full-duplex, clocked, four-wire (MOSI/MISO/SCK/CS). Maximum speeds rose with MCU capabilities: 1 MHz in the 1980s (68HC11), 25 MHz by 2000, 100+ MHz on modern ARM Cortex-M7 parts. Quad-SPI (4-bit data) and Octal-SPI extensions for NOR flash memory pushed effective bandwidth past 500 MB/s.

About This Calculator

Enter SPI clock, MCU clock-to-output delay tCO (from MCU datasheet AC characteristics), slave setup/hold time (from peripheral datasheet), and PCB trace length. The tool computes clock period, setup margin = T/2 − tCO − t_trace − t_setup, and hold margin.

If setup margin is negative, reduce SPI clock. If hold margin negative, trace is too long or tCO too fast — shorten trace or add intentional delay. For source-synchronous SPI (QSPI DDR), timing budget is different; consult the controller datasheet. Everything runs client-side.

Frequently Asked Questions

Why a budget?

At high SPI speeds (20-80 MHz), clock period approaches driver + receiver + trace delays. Setup and hold windows shrink. A budget checks if worst-case timings still leave positive margin.

Typical limits?

Small SPI flash (e.g., W25Q64): 104 MHz clock, 7 ns setup, 2 ns hold. MCU SPI driver: 5-15 ns output delay (from SCK to data-out). Total round-trip must fit within half the SPI period.

Mode 0/1/2/3?

Clock polarity (CPOL) and phase (CPHA) determine edge used for sampling. Most chips use Mode 0 (sample on rising, shift on falling). Mode number doesn\'t change timing budget, only edge polarity.

Common Use Cases

SPI Flash

STM32 + W25Q64: 80 MHz SCK, ≈ 12 ns period. tCO (MCU) 10 ns + 2 ns trace + 7 ns setup = 19 ns ≫ 12 ns. → reduce clock or use DDR mode.

DAC/ADC

AD9106 at 40 MHz: 25 ns period, 5 ns tCO, 4 ns setup = healthy 16 ns margin.

Display Driver

ILI9341 display at 40 MHz: similar safe margin for 4-inch LCD refresh.

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