SPI Timing Budget Calculator
Compute SPI timing budget: setup, hold, propagation delay, trace delay, and driver/receiver spec to verify valid operation at target clock.
How to Use
- Enter SPI clock, driver output delay (tCO), receiver setup/hold spec (ts, th).
- Enter PCB trace delay (1-6 ps/mm typical).
- Tool verifies worst-case margin.
Show Work
Formulas
History of SPI
Motorola introduced SPI in the late 1970s for Motorola MC68xx microcontroller peripheral interconnect. Unlike I2C, SPI prioritizes speed over pin count - full-duplex, clocked, four-wire (MOSI/MISO/SCK/CS). Maximum speeds rose with MCU capabilities: 1 MHz in the 1980s (68HC11), 25 MHz by 2000, 100+ MHz on modern ARM Cortex-M7 parts. Quad-SPI (4-bit data) and Octal-SPI extensions for NOR flash memory pushed effective bandwidth past 500 MB/s.
About This Calculator
Enter SPI clock, MCU clock-to-output delay tCO (from MCU datasheet AC characteristics), slave setup/hold time (from peripheral datasheet), and PCB trace length. The tool computes clock period, setup margin = T/2 − tCO − t_trace − t_setup, and hold margin.
If setup margin is negative, reduce SPI clock. If hold margin negative, trace is too long or tCO too fast — shorten trace or add intentional delay. For source-synchronous SPI (QSPI DDR), timing budget is different; consult the controller datasheet. Everything runs client-side.
About the SPI Timing Budget Calculator
The SPI Timing Budget Calculator is a free tool for electronics and circuit design. It runs right in your web browser, so there is nothing to download. Compute SPI timing budget: setup, hold, propagation delay, trace delay, and driver/receiver spec to verify valid operation at target clock.
How it works
Type your numbers into the boxes. The answer shows up right away — you do not have to press a button. If you change a number, the answer changes too. So you can try different numbers and watch what happens, or check an answer you worked out yourself. Just make sure each box has the right kind of number in it.
Want the deeper story? The Knowledge Base explains the ideas behind the tools in more detail.
Frequently Asked Questions
Why a budget?
At high SPI speeds (20-80 MHz), clock period approaches driver + receiver + trace delays. Setup and hold windows shrink. A budget checks if worst-case timings still leave positive margin.
Typical limits?
Small SPI flash (e.g., W25Q64): 104 MHz clock, 7 ns setup, 2 ns hold. MCU SPI driver: 5-15 ns output delay (from SCK to data-out). Total round-trip must fit within half the SPI period.
Mode 0/1/2/3?
Clock polarity (CPOL) and phase (CPHA) determine edge used for sampling. Most chips use Mode 0 (sample on rising, shift on falling). Mode number doesn\'t change timing budget, only edge polarity.
How do I use the SPI Timing Budget Calculator?
Just type your numbers. The answer shows up right away — there is no button to press. Change anything and it updates by itself.
Is it free? Does it work without internet?
Yes to both. It is free with no sign-up, and once the page has loaded it keeps working even with no internet.
Where does my data go?
Nowhere — every calculation runs on your own device. Nothing you enter is uploaded, logged, or stored.
Common Use Cases
SPI Flash
STM32 + W25Q64: 80 MHz SCK, ≈ 12 ns period. tCO (MCU) 10 ns + 2 ns trace + 7 ns setup = 19 ns ≫ 12 ns. → reduce clock or use DDR mode.
DAC/ADC
AD9106 at 40 MHz: 25 ns period, 5 ns tCO, 4 ns setup = healthy 16 ns margin.
Display Driver
ILI9341 display at 40 MHz: similar safe margin for 4-inch LCD refresh.
Last updated: